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[ak4686] ms1243-e-01 2010/10 - 1 - general description the ak4686 is a single chip audio codec that inclu des one stereo adc and two st ereo dacs in addition to the input selector and the line drivers. the interf aces of adc/dac can acc ept up to 24bit input data and support asynchronous operation. both the input stereo selector and output drivers support ground reference i/o to remove ac-coupling capacitors and r educing external parts. the ak4686 has a dynamic range of 96db for adc, 100db for dac, and it is well suitable for digital tv and home theater systems. features ? asynchronous operation between port 1(adc and dac1) and port 2 (dac2) ? 6:1 capless stereo line input selector ? 24bit stereo adc - 64x oversampling - sampling rate up to 48khz - linear phase digital anti-alias filter - s/(n+d): 88db - dynamic range, s/n: 96db - digital hpf for offset cancellation ? 24bit two stereo dac - 128x oversampling - sampling rate up to 192khz - 24bit 8 times digital filter - s/(n+d): 88db - dynamic range, s/n: 100db - de-emphasis filter - analog soft mute ? high jitter tolerance ? ttl level digital i/f ? external master clock input: 256fs, 384fs, 512fs 768fs (fs=32khz 48khz) 128fs, 192fs, 256fs 384fs (fs=64khz 96khz) 128fs, 192fs (fs=128khz ~ 192khz) ? 2 audio serial i/f (port1, port2) - master/slave mode (port1) - i/f format port2: msb, lsb justified (16/24 bit), i2s port1: msb, lsb justified (16/24 bit), i2s ? i 2 c bus p i/f for mode setting ? operating voltage: - digital i/o: 3.0v 3.6v - charge pump: 3.0v 3.6v - analog: 3.0v 3.6v ? package: 48pinlqfp ak4686 multi-channel codec with capless stereo selector
[ak4686] ms1243-e-01 2010/10 - 2 - 2ch adc lin1 lin2 lin3 lin4 lin5 lin6 lout1 rout1 cvee cp cn lout2 rout2 mclk1 bick1 lrck1 sdto1 sdti1 ms1 port1 2vrms hpf serial i/f 2vrms charge pump rin1 rin2 rin3 rin4 rin5 rin6 2ch dac pwad bit mclk2 bick2 lrck2 sdti2 port2 2ch dac serial i/f pwad bit or pwda1 bit pdn pin sda scl mt1n mt2n pdn control i/f a vdd1 vss1 cvdd vss2 a vdd2 vss3 dvdd vss4 pwda1 bit pwda2 bit a nalog soft mute a nalog soft mute cad0 cad1 ak4686 block diagram
[ak4686] ms1243-e-01 2010/10 - 3 - ordering guide ak4686eq -20 +85 c 48pin lqfp (0.5mm pitch) AKD4686 evaluation bo ard for the ak4686 pin layout 37 rin3 36 38 lin1 39 lin2 40 rin2 41 nc 42 43 rin1 44 lin3 45 lin4 46 rin4 47 3 5 34 33 32 31 v ss4 30 dvdd 29 28 27 26 1 lin5 2 lin6 3 rin5 4 rin6 5 avdd1 6 vss1 7 lout1 8 9 rout1 10 lout2 11 23 22 21 20 19 18 17 16 15 14 13 cvdd vss3 cn cp cvee ak4686eq top v ie w nc 48 12 24 25 nc vss2 mt2n mt1n mc lk1 sdti1 sd a bick1 sdto ms1 lr ck1 scl nc nc rout2 avdd 2 bick2 lrc k2 sdti2 mclk2 pdn nc
[ak4686] ms1243-e-01 2010/10 - 4 - pin/function no. pin name i/o function 1 lin5 i lch input 5 pin 2 rin5 i rch input 5 pin 3 nc - this pin must be connected to the ground. 4 lin6 i lch input 6 pin 5 rin6 i rch input 6 pin 6 avdd1 - adc&dac1 analog power supply pin, 3.0v 3.6v 7 vss1 - adc&dac1 analog ground pin, 0v 8 lout1 o lch analog output pin1 9 rout1 o rch analog output pin1 10 lout2 o lch analog output pin2 11 rout2 o rch analog output pin2 12 avdd2 - dac2 analog power supply pin, 3.3v 3.6v 13 vss2 - dac2 analog ground pin, 0v 14 cvee o charge pump circuit negative voltage output pin (for analog input/output) 15 cn i negative charge pump capacitor terminal pin (for analog input/output) 16 vss3 - charge pump circuit analog ground pin, 0v (for analog input/output) 17 cp i positive charge pump capacitor terminal pin (for analog input/output) 18 cvdd - charge pump circuit positive power supply pin 3.0v 3.6v (for analog input/output) 19 pdn i power-down mode & reset pin when ?l?, the ak4686 is powered-down, all registers are reset. and then all digital output pins go ?l?. the ak4686 must be reset once upon power-up. 20 sdti2 i audio serial data input pin (for port2) 21 lrck2 i input channel clock pin (for port2) 22 mclk2 i dac2 master clock input pin (for port2) 23 bick2 i audio serial data clock pin (for port2) 24 nc - this pin must be connected to the ground. 25 mt2n i dac2 mute pin ?h?: normal operation ?l?: mute 26 ms1 i port1 master mode select pin. ?l?(connected to the ground): slave mode. ?h?(connected to dvdd) : master mode. 27 sdti1 i audio serial data input pin (for port1) 28 mclk1 i adc&dac1 master clock input pin (for port1) 29 mt1n i dac1 mute pin ?h?: normal operation ?l?: mute 30 dvdd - digital power supply pin, 3.0v 3.6v 31 vss4 - digital ground pin, 0v 32 sdto o audio serial data output 1 pin (for port1) 33 lrck1 i/o channel clock 1 pin (for port1) 34 bick1 i/o audio serial data clock 1 pin (for port1) 35 sda i/o control data pin 36 scl i control data clock pin 37 lin1 i lch input 1 pin 38 rin1 i rch input 1 pin 39 nc - this pin must be connected to the ground. 40 lin2 i lch input 2 pin 41 rin2 i rch input 2 pin 42 nc - this pin must be connected to the ground.
[ak4686] ms1243-e-01 2010/10 - 5 - pin/function (continued) no. pin name i/o function 43 lin3 i lch input 3 pin 44 rin3 i rch input 3 pin 45 nc - this pin must be connected to the ground. 46 lin4 i lch input 4 pin 47 rin4 i rch input 4 pin 48 nc - this pin must be connected to the ground. note: all digital input pins must not be left floating. handling of unused pin the unused i/o pins must be processed appropriately as below. classification pin name setting analog lout1-2, rout1-2, lin1-6, rin1-6 these pins must be open. sdto1, lrck1(master), bick1(mast er) these pins must be open. mclk1-2, lrck1(slave), lrck2, bick1(slave), bick2, sdti1-2, ms1, cad0 these pins must be connected to vss4. digital sda, scl, mt1n, mt2n these pins must be pulled-up to dvdd. - nc these pins should be connected to the ground.
[ak4686] ms1243-e-01 2010/10 - 6 - absolute maximum ratings (vss1=vss2=vss3=vss4 =0v; note 1 ) parameter symbol min max units power supply dvdd avdd1 avdd2 cvdd -0.3 -0.3 -0.3 -0.3 4.0 4.0 4.0 4.0 v v v v input current (any pins except for supplies) iin - 10 ma digital input voltage (mclk1-2, pdn, lrck1-2, bick1-2, sdti1-2, sda, scl, ms1, cad0, mt1n and mt2n pins ) vind -0.3 dvdd+0.3 v analog input voltage (lin1-6, rin1-6 pins) vina -0.3 avdd1+0.3 v ambient operating temperature ta -20 85 c storage temperature tstg -65 150 c note 1. vss1, vss2, vss3 and vss4 must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1=vss2=vss3=vss4= 0v; note 1 ) parameter symbol min typ max units power supply ( note 2 ) dvdd avdd1 avdd2 cvdd 3.0 3.0 3.0 3.0 3.3 3.3 3.3 3.3 3.6 3.6 3.6 3.6 v v v v note 2. the avdd1, avdd2 and cvdd must be the same voltage. the voltage difference between dvdd and other voltages (avdd1, avdd2 and cvdd) must be less than 0.3v. *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[ak4686] ms1243-e-01 2010/10 - 7 - analog characteristics (ta=25 c; avdd1=avdd2= cvdd = dvdd= 3.3v; vss1=vss2= vss3=vss4=0v; fs=48khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency = 20hz 20khz at fs=48khz, 20hz~40khz at fs=96khz; 20hz~40khz at fs=192khz, all blocks are synchronized, unless otherwise specified) parameter min typ max units input impedance 12 16.4 k analog input (lin1-6, rin1-6pin) to adc analog input characteristics resolution 24 bits s/(n+d) (-1dbfs) fs=48khz 75 88 db dr (-60dbfs) fs=48khz, a-weighted 88 96 db s/n (input off) fs=48khz, a-weighted 88 96 db interchannel isolation ( note 3 ) 90 100 db interchannel gain mismatch 0 0.6 db gain drift 50 - ppm/ c input voltage ain= 2.2 x avdd1/3.3 2 2.2 2.4 vrms power supply rejection ( note 4 ) 50 db dac to analog output (lout1-2, rout1-2 pin) characteristics resolution 24 bits s/(n+d) (0dbfs) fs=48khz fs=96khz fs=192khz 76 - - 88 84 84 db db db dr (-60dbfs) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted fs=192khz fs=192khz, a-weighted 94 - - - - 100 96 100 96 100 db db db db db s/n (?0? data) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted fs=192khz fs=192khz, a-weighted 94 - - - - 100 96 100 96 100 db db db db db interchannel isolation 90 100 db interchannel gain mismatch 0 0.5 db gain drift 50 - ppm/ c output voltage aout= 2 x avdd1(avdd2)/3.3 1.90 2 2.15 vrms load resistance (ac load) 5 k load capacitance (c1) 30 pf load resistance (r1) 446.5 470 load capacitance (c2) 1 1.5 nf power supply rejection ( note 4 ) 50 db note 3. this value is the channel isolation for all other channels when inputting full scale signal to one channel. note 4. psr is applied to avdd1, avdd2, dvdd and cvdd with 1khz, 50mvpp. r1 c2 analog out c1 lout/rout1,2 pin figure 1. lineout circuit example
[ak4686] ms1243-e-01 2010/10 - 8 - power supplies parameter min typ max units power supply current normal operation (pdn pin = ?h?) dvdd+avdd1+avdd2 cvdd power-down mode (pdn pin = ?l?; note 5 ) dvdd+avdd1+avdd2+cvdd 26 8 10 34 13 100 ma ma a note 5. all digital inputs including clock pins (mclk1-2, bick1-2, lrck1-2 and sdti1-2) are held at dvdd or vss4. filter characteristics (ta=-20 c ~+85 c; avdd1=avdd2= cvdd = dvdd= 3.3v; fs=48khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 6 ) 0.1db -0.2db -3.0db pb 0 - - 19.9 22.9 18.5 - - khz khz khz stopband sb 27.9 khz stopband attenuation sa 61 db group delay ( note 7 ) gd 15.7 1/fs group delay distortion gd 0 s adc digital filter (hpf): frequency response ( note 6 ) -3db -0.1db fr 1.0 6.5 hz hz dac digital filter: passband ( note 6 ) -0.1db -6.0db pb 0 - 24.0 21.8 - khz khz stopband sb 26.2 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay ( note 7 ) gd 19 1/fs dac digital filter + analog filter: frequency response: 0 20.0khz 40.0khz ( note 8 ) 80.0khz ( note 8 ) fr fr fr 0.2 0.3 1.0 db db db note 6. the passband and stopband frequencies scale with fs. for example, 21.8khz at ?0.1db is 0.454 x fs (dac). the reference frequency of these responses is 1khz. note 7. the calculating delay time occurred at digital filte ring. this time is from setting the input of analog signal to setting the 24bit data of both channels to the output register of port1. for dac, this time is from setting the 20/24bit data of both channels on input register of port2 to the output of analog signal. note 8. 40.0khz@fs=96khz, 80.0khz@fs=192khz.
[ak4686] ms1243-e-01 2010/10 - 9 - dc characteristics (ta=-20 c ~+85 c; avdd1=avdd2=cvdd = dvdd= 3.3v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%dvdd - - - - 30%dvdd v v high-level output voltage ( iout=-400 a) low-level output voltage (iout= -400 a(except sda pin), 3ma(sda pin)) voh vol dvdd-0.4 - - - 0.4 v v input leakage current iin - - 10 a switching characteristics (ta=-20 c ~+85 c; avdd1=avdd2=cvdd = dvdd= 3.3v; c l = 20pf (except for sda pin), cb=400pf(sda pin)) parameter symbol min typ max units master clock timing frequency duty feclk declk 8.192 40 50 36.864 60 mhz % master clock 256fsn, 128fsd: pulse width low pulse width high 384fsn, 192fsd: pulse width low pulse width high 512fsn, 256fsd, 128fsq: pulse width low pulse width high 768fsn, 384fsd, 192fsq: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 8.192 27 27 12.288 20 20 16.384 15 15 24.576 10 10 12.288 18.432 24.576 36.864 mhz ns ns mhz ns ns mhz ns ns mhz ns ns lrck1/2timing (slave mode) normal mode normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 32 64 128 45 48 96 192 55 khz khz khz % lrck1 timing (master mode) normal mode normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 32 64 128 50 48 96 192 khz khz khz % power-down & reset timing pdn pulse width ( note 9 ) pdn ? ? to sdto1 valid ( note 10 ) tpd tpdv 150 296 ns 1/fs note 9. the ak4686 can be reset by bringing the pdn pin = ?l?. note 10. after a rising edge of pdn, the internal counter starts by divided clock of mclk and adc power down is released by a falling edge of cvee after 256/fs on lrck, then sdto1 is output 40/fs later.
[ak4686] ms1243-e-01 2010/10 - 10 - parameter symbol min typ max units audio interface timing (slave mode) port1(dac1), port2 (dac2) bick1, 2 period bick1, 2 pulse width low pulse width high lrck1, 2 edge to bick1, 2 ? ? ( note 11 ) bick1, 2 ? ? to lrck1, 2 edge ( note 11 ) sdti1, 2 hold time sdti1, 2 setup time tbck tbckl tbckh tlrb tblr tsdh tsds 81 32 32 20 20 10 10 ns ns ns ns ns ns ns port1 (adc) bick1 period bick1 pulse width low pulse width high lrck1 edge to bick1 ? ? ( note 11 ) bick1 ? ? to lrck1 edge ( note 11 ) lrck1 to sdto1 (msb) bick1 ? ? to sdto1 tbck tbckl tbckh tlrb tblr tlrs tbsd 324 128 128 80 80 80 80 ns ns ns ns ns ns ns audio interface timing (master mode) bick1 frequency bick1 duty bick1 ? ? to lrck1 edge bick1 ? ? to sdto1 sdti1 hold time sdti1 setup time fbck dbck tmblr tbsd tsdh tsds -20 25 10 64fs 50 20 20 hz % ns ns ns ns control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 12 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 - 0 400 - - - - - - - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf note 11. bick rising edge must not occur at the same time as lrck edge. note 12. data must be held for sufficient time to bridge the 300 ns transition time of scl. note 13. i 2 c-bus is a trademark of nxp b.v.
[ak4686] ms1243-e-01 2010/10 - 11 - timing diagram 1/fclk tclkl vih tclkh mclk vil 1/fsn, 1/fsd, 1/fsq lrck vih vil tbck tbckl vih tbckh bick vil clock timing (normal mode) tlrb lrck vih bick vil tlrs sdto 50% tvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing lrck= lrck1, lrck2 bick= bick1, bick2 sdti= sdti1/2 sdto= sdto1.
[ak4686] ms1243-e-01 2010/10 - 12 - lrck bick sdto tbsd tmblr 50% tvdd 50% tvdd 50% tvdd audio interface timing (master mode) tpd vil pdn tpdv sdto 50% tvdd vih power down & reset timing thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing
[ak4686] ms1243-e-01 2010/10 - 13 - operation overview system clock the ak4686 has two audio serial interfaces (port1 and port 2) which can be operated as ynchronously. at each port, the external clocks, which are required to operate th e ak4686, are mclk1 (mclk2), lrck1 (lrck2) and bick1 (bick2). the mclk1 (mclk2) must be synchronized with lrck1 (lrck2) but the phase is not critical. the port2 is an audio data interfaces for dac2, the port1 is for adc and dac1. the ak4686 is automatically powered down, then the adc output becomes ?0? data and dac output is pulled down (vss) when mclk1 (mclk2) is stopped more than 2s or bick1 or lrck1 (bick2 or lrck2) are stopped more than 1024*mclk cycles during an operation (pdn pin = ?h?) . the power down state is re leased when mclk1, bick1 and lrck1 (mclk2, bick2 and lrck2) are input and the ak4686 starts an operation. when reset is released (pdn pin = ?l? ?h?), such as when power up the device, the ak46 86 is in power down state until mclk1 (mclk2) is input. the ak4686 is reset automatically and the phase is synchroni zed by a phase detection circu it when internal timings are unsynchronized by clock change during an operation. master/slave mode the ms1 pin controls master/slave mode of the port1. th e port2 supports slave mode only. in master mode, lrck1 pin and bick1 pin are output pins. in slave mode, lrck1, lrck2 pins and bick1, bick2 pins are input pins ( table 1 ). pdn pin ms1 pin port1 (adc, dac1) bick1, lrck1 port2 (dac2) bick2, lrck2 l input (slave mode) input (slave mode) l h output ?l?(master mode) input (slave mode) table 1. master/salve mode
[ak4686] ms1243-e-01 2010/10 - 14 - port1 (adc, dac1) clock control in master mode (ms1 pin = ?h?), the cks12-0 bits select the clock frequency ( table 2 ). the external clock (mclk1) must always be supplied except in power-down mode (pdn pin = ?l? or pwad bit, pwda1 bit = ?0?). the adc is in power-down mode until mclk1 is supplied. cks12 cks11 cks10 sampling speed (fs) master clock speed 0 0 0 normal or double 32khz~48khz, 64khz~96khz 256fs (default) 0 0 1 normal or double 32khz~48khz, 64khz~96khz 384fs 0 1 0 normal 32khz~48khz 512fs 0 1 1 normal 32khz~48khz 768fs 1 0 0 double or quad 64khz~96khz, 128khz~192khz 128fs 1 0 1 double or quad 64khz~96khz, 128khz~192khz 192fs 1 1 x x n/a table 2. port1(adc, dac1) master clock control (master mode) in slave mode (ms1 pin = ?l?), external clocks (mclk1, bi ck1, lrck1) must always be present whenever the adc is in normal operation mode (pdn pin = ?h? or pwad bit = pwda1 bit = ?1?). the master clock (mclk1) must be synchronized with lrck1 but the phase is not critical. if these clocks are not provided, the adc may draw excess current because the device utilizes dynamic refreshed logic internally. if the external clocks are not present, the adc and dac1 must be in power-down mode (pdn pin = ?l? or pwad bit = pwda1 bit = ?0?) or in reset mode (rstn bit = ?0?). after exiting reset at power-up and etc., adc is in power-down mode until mclk1 and lrck1 are input. there are two modes for controlling the sampling speed of adc and dac1. one is manual setting mode (acks1 bit = ?0?) using the dfs11-10 bits, and the other is auto settin g mode (acks1 bit = ?1?). the adc only supports normal speed mode, and it is powered-down in double speed mode and quad speed mode. 1. manual setting mode (acks1 bit = ?0?) when the acks1 bit = ?0?, adc and dac1 is in manual setting mode and the sampling speed is selected by dfs11-10 bits ( table 3 ). dfs11 dfs10 adc sampling speed (fs) dac1 sampling speed (fs) 0 0 normal speed mode 32khz~48khz normal speed mode 32khz~48khz (default) 0 1 power down double speed mode 64khz~96khz 1 0 power down quad speed mode 128khz~192khz 1 1 not available table 3. port1(adc, dac1) sampling speed (acks1bit = ?0?, manual setting mode) lrck1 mclk1 (mhz) bick1 (mhz) fs 256fs 384fs 512fs 768fs 64fs 32.0khz 8.1920 12.2880 16.3840 24.5760 2.0480 44.1khz 11.2896 16.9344 22.5792 33.8688 2.8224 48.0khz 12.2880 18.4320 24.5760 36.8640 3.0720 table 4. adc, dac1 system clock example (adc, dac1 normal speed mode @manual setting mode)
[ak4686] ms1243-e-01 2010/10 - 15 - lrck1 mclk1 (mhz) bick1 (mhz) fs 128fs 192fs 256fs 384fs 64fs 88.2khz 11.2896 16.9344 22.5792 33.8688 5.6448 96.0khz 12.2880 18.4320 24.5760 36.8640 6.1440 table 5. dac1 system clock example (dac1 double speed mode @manual setting mode) lrck1 mclk1 (mhz) bick1 (mhz) fs 128fs 192fs 256fs 384fs 64fs 176.4khz 22.5792 33.8688 - - 11.2896 192.0khz 24.5760 36.8640 - - 12.2880 table 6. dac1 system clock example (dac1 quad speed mode @manual setting mode) 2. auto setting mode (acks1 bit = ?1?) when the acks1 bit = ?1?, adc and dac1 are in auto setting mode and the sampling speed is selected automatically by the ratio of mclk1/lrck1, as shown in the table 7 and the internal master clock is set to the appropriate frequency ( table 8 ). the adc only supports normal speed mode, and it is powered-down in double speed mode and quad speed mode. in this mode, the settings of dfs11-10 bits are ignored. ( table 5 , table 6 ) mclk1 lrck1 adc sampling speed dac sampling speed 512fs, 768fs 32khz~48khz normal speed mode normal speed mode 256fs, 384fs 64khz~96khz power down double speed mode 128fs, 192fs 120khz~192khz power down quad speed mode table 7. port1(adc,dac1) sampling speed (acks1 bit = ?1?, auto setting mode) lrck1 mclk1 (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs adc sampling speed dac1 sampling speed 32.0khz - - - - 16.3840 24.5760 44.1khz - - - - 22.5792 33.8688 48.0khz - - - - 24.5760 36.8640 normal normal 88.2khz - - 22.5792 33.8688 - - 96.0khz - - 24.5760 36.8640 - - power down double 176.4khz 22.5792 33.8688 - - - - 192.0khz 24.5760 36.8640 - - - - power down quad table 8. port1 (adc, dac1) system clock example (auto setting mode)
[ak4686] ms1243-e-01 2010/10 - 16 - port2 (dac2) clock control external clocks (mclk2, bick2 and lrck 2) must always be present whenever the dac is in normal operation mode (pdn pin = ?h? or pwda2 bit= ?1?). the master clock mclk2 must be synchronized with lrck2 but the phase is not critical. if these clocks are not provided , the dac may draw excess current because the device utilizes dynamic refreshed logic internally. if the external clocks are not present, the dac must be in power-down mode (pdn pin = ?l? or pwda2 bit = ?0?) or in reset mode (rstn bit = ?0?). after exiting reset at power-up and etc., th e dac is in power-down mode until mclk2 and lrck2 are input. there are two modes for controlling the sampling speed of dac 2. one is the manual setting mode (acks2 bit = ?0?) using the dfs21-20 bits, and the other is auto setting mode (acks2 bit = ?1?). 1. manual setting mode (acks2 bit = ?0?) when the acks2 bit = ?0?, dac2 is in manual setting mode and the sampling speed is selected by dfs21-20 bits ( table 9 ). dfs21 dfs20 dac2 sampling speed (fs) 0 0 normal speed mode 32khz~48khz 0 1 double speed mode 64khz~96khz (default) 1 0 quad speed mode 128khz~192khz 1 1 not available - table 9. port2(dac2) sampling speed (acks2 bit = ?0?, manual setting mode) lrck2 mclk2 (mhz) bick2 (mhz) fs 256fs 384fs 512fs 768fs 64fs 32.0khz 8.1920 12.2880 16.3840 24.5760 2.0480 44.1khz 11.2896 16.9344 22.5792 33.8688 2.8224 48.0khz 12.2880 18.4320 24.5760 36.8640 3.0720 table 10. dac2 system clock example (dac normal speed mode @manual setting mode) lrck2 mclk2 (mhz) bick2 (mhz) fs 128fs 192fs 256fs 384fs 64fs 88.2khz 11.2896 16.9344 22.5792 33.8688 5.6448 96.0khz 12.2880 18.4320 24.5760 36.8640 6.1440 table 11. dac2 system clock example (dac double speed mode @manual setting mode) lrck2 mclk2 (mhz) bick2 (mhz) fs 128fs 192fs 256fs 384fs 64fs 176.4khz 22.5792 33.8688 - - 11.2896 192.0khz 24.5760 36.8640 - - 12.2880 table 12. dac2 system clock example (dac quad speed mode @manual setting mode)
[ak4686] ms1243-e-01 2010/10 - 17 - 2. auto setting mode (acks2 bit = ?1?) when the acks2 bit = ?1?, dac2 is in auto setting mode and the sampling speed is selected automatically by the ratio of mclk2/lrck2, as shown in the table 13 and the internal master clock is set to the appropriate frequency ( table 14 ). in this mode, the settings of dfs1-0 bits are ignored. mclk2 dac sampling speed (fs) lrck2 512fs, 768fs normal speed mode 32khz~48khz 256fs, 384fs double speed mode 64khz~96khz 128fs, 192fs quad speed mode 128khz~192khz table 13. port2(dac2) sampling speed (acks2 bit = ?1?, auto setting mode) lrck2 mclk2 (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs sampling speed 32.0khz - - - - 16.3840 24.5760 44.1khz - - - - 22.5792 33.8688 48.0khz - - - - 24.5760 36.8640 normal 88.2khz - - 22.5792 33.8688 - - 96.0khz - - 24.5760 36.8640 - - double 176.4khz 22.5792 33.8688 - - - - 192.0khz 24.5760 36.8640 - - - - quad table 14. port2 (dac2) system clock example (auto setting mode) de-emphasis filter the ak4686 includes a digital de-emphasis filter (tc=50/15 s) by iir filter. this filter corresponds to three sampling frequencies (32khz, 44.1khz, 48khz). de -emphasis filter is off in double sp eed mode and quad speed mode. de- emphasis of each dac can be set individually by registers. mode dem11 (dem21) dem10 (dem20) dem 0 0 0 44.1khz 1 0 1 off 2 1 0 48khz 3 1 1 32khz (default) table 15. de-emphasis control adc digital high pass filter the adc has a digital high pass filter for dc offset cancellation. the cut-off frequency of the hpf is 1.0hz at fs=48khz and scales with sampling rate (fs).
[ak4686] ms1243-e-01 2010/10 - 18 - audio serial interface format each port1/2 can select independent au dio interface format. the dif11-10 bits control the audio format for port1. the dif21-20 bits control the audio format for port2. in all modes the serial data is msb-first, 2?s complement format. the sdto1 pin is clocked out on the falling edge of bick1 pi n and the sdti1-2 pins are latched on the rising edge of bick1-2 pins. 1. port1(adc,dac1) setting the ms1 pin and dif11-10 bits select following four serial data formats ( table 16 ). lrck1 bick1 mode ms1 pin dif11 bit dif10 bit sdto sdti1 l/r i/o speed i/o 0 0 0 0 24/16bit, l j 16bit, r j h/l i 48fs or 32fs i 1 0 0 1 24bit, l j 24bit, r j h/l i 48fs i 2 0 1 0 24bit, l j 24bit, l j h/l i 48fs i 3 0 1 1 24bit, i 2 s 24bit, i 2 s l/h i 48fs i (default) 4 1 0 0 24bit, l j 16bit, r j h/l o 64fs o 5 1 0 1 24bit, l j 24bit, r j h/l o 64fs o 6 1 1 0 24bit, l j 24bit, l j h/l o 64fs o 7 1 1 1 24bit, i 2 s 24bit, i 2 s l/h o 64fs o (default) table 16. audio interface form at (normal mode, x: don?t care, l j: le ft justified, r j: right justified.) 2. port2(dac2) setting the dif21-20 bits select following four serial data formats ( table 17 ). lrck2 bick2 mode dif21 bit dif20 bit sdti2 l/r i/o speed i/o 0 0 0 16bit, right justified h/l i 48fs or 32fs i 1 0 1 24bit, right justified h/l i 48fs i 2 1 0 24bit, left justified h/l i 48fs i 3 1 1 24bit, i 2 s l/h i 48fs i (default) table 17. audio interface format
[ak4686] ms1243-e-01 2010/10 - 19 - lrck bick(64fs) sdto(o) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sdti(i) 1 14 0 15 8 7 1 14 0 15 8 7 lch data rch data don?t care don?t care 12 11 10 sdto-23:msb, 0:lsb; sdti-15:msb, 0:lsb figure 2. mode 0/4 timing lrck bick(64fs) sdto(o) 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti(i) 1 22 0 23 8 7 1 22 0 23 8 7 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 3. mode 1/5 timing lrck bick(64fs) sdto(o) 0 1 2 21 22 23 24 31 0 1 2 0 23 1 22 1 23 22 23 sdti(i) 22 23 0 22 23 23:msb, 0:lsb lch data rch data don?t care 2 2 1 28 29 30 23 0 22 23 24 31 1 0 don?t care 2 21 28 29 30 0 figure 4. mode 2/6 timing lrck bick(64fs) sdto(o) 0 1 2 3 22 23 24 25 0 0 1 sdti(i) 31 29 30 23 22 1 22 23 0 23:msb, 0:lsb lch data rch data don?t care 2 2 1 0 2 3 22 23 24 25 0 31 29 30 23 22 1 22 23 0 don?t care 2 21 0 1 figure 5. mode 3/7 timing
[ak4686] ms1243-e-01 2010/10 - 20 - analog soft mute function lout1, rout1/lout2, rout2 are muted in soft transition wh en the mt1n/2n pins are set to ?l? from ?h?. after the soft mute transition is finished, the dac and lineout are in powered-down mode and output ground level voltage (vss1/vss3). the transition time is set by amts1-0 bits. cl ocks and data must always be supplied until soft mute transition is finished. the dac and lineout return to a normal operation and start digital to analog conversion when the mt1n/2n pins are set to ?h?. mute is cancelled in soft transition after initializing time of dac. when the mt1n/2n pin = ?l? or mt1n/2n bit = ?0?, lout1, rout1/lout2, rout2 are muted. normal operation init cycle mt1n/2n pin gd (1) (2) lout1,rout1/ lout2,rout2 dac internal state 512/fs power(pdn pin) (3) mt1n/2n bit normal operation (1) click noise may occur if each pow er supply (dvdd, avdd1/2 and cvdd) is off during mute period. power supplies should be on longer than the soft mute time set by amts1-0 bits. (2) soft mute time is set by amts1-0 bits (2). (3) soft mute time is set by amts1-0 bits (3). figure 6. mute sequence example soft mute time (fs=48khz) (2) (3) amts2 amts1 amts0 mt1n/2n pin mt1n/2n bit mt1n/2n 0 0 0 16ms 16ms 16ms 0 0 1 32ms 32ms 32ms (default) 0 1 0 64ms 64ms 64ms 0 1 1 128ms 128ms 128ms 1 0 0 256ms 256ms 256ms 1 0 1 8ms 16ms 16ms 1 1 x 2ms 16ms 16ms (x: don?t care) table 18. soft mute time select (@48khz) when amts2-0 bits = ?101? or ?11x?, the soft mute time by mt1n/2n pin and by mt1n/2n bit are different.
[ak4686] ms1243-e-01 2010/10 - 21 - input selector the ak4686 has 6:1 stereo input selectors. atin3-0 bits control each input channel. ( table 19 ) ain3 bit ain2 bit ain1 bit ain0 bit input selector 0 0 0 0 lin1 / rin1 (default) 0 0 0 1 lin2 / rin2 0 0 1 0 lin3 / rin3 0 0 1 1 lin4 / rin4 0 1 0 0 lin5 / rin5 0 1 0 1 lin6 / rin6 0 1 1 0 (reserved) 0 1 1 1 (reserved) 1 x x x mute table 19. input selector (for adc, x: don?t care)
[ak4686] ms1243-e-01 2010/10 - 22 - charge pump circuit the internal charge pump circuit generates negative voltage (cvee) from cvdd voltage for analog input and output. the power up time of charge pump circuit is 5.3ms@48khz. when pwad and pwda1/2 bits = ?1?, the adc and dac1/2 are powered-up after the charge pump circuit is powered-up. analog input/output (lin1-6/rin1-6, lout1-2/rout1-2 pins) power supply voltage for analog input/output is applied fr om a regulator for positive power and a charge-pump for negative power. the regulator is driven by avdd2 and the charge-pump1 is driven by cvdd. the analog input/output is single-ended and centered on 0v (vss3). therefore, the capacitor for ac-coupling can be removed. the minimum load resistance is 5k . when the dac input signal level is 0dbfs, the output voltage is 2vrms. v system reset when power-up the ak4686, the pdn pin should be ?l? and changed to ?h? after all power supplies (dvdd, avdd1, avdd2 and cvdd) are supplied. after this reset is released (pdn pin = ?l? : ?h?), all blocks are in power-down mode. this ensures that all internal registers reset to their initial values.
[ak4686] ms1243-e-01 2010/10 - 23 - power on/off sequence the each block of the ak4686 is placed in power-down mode by bringing the pdn pin to ?l? and both digital filters are reset at the same time. the pdn pin =?l? also reset the contro l registers to their default values. in power-down mode, the dac1/2 outputs 0v and the sdto1 pin goes to ?l?. this reset must always be executed after power-up. in slave mode, after exiting reset at power-up and etc., th e adc/dac1/dac2 starts operation from the rising edge of lrck1/2 after mlck1/2 inputs. the ak4686 is in power-down mode until mclk1/2 and lrck1/2 are input. the analog initialization cycle of adc starts after exiting the power-down mode. theref ore, the output data, sdto1 becomes available after 514/fs cycles of lrck1 clock. in cas e of the dac1/2 an analog in itialization cycle starts after exiting the power-down mode. the analog out puts are 0v during the initialization. figure 7 shows the sequences of the power-down and the power-up. the adc and all dacs can be powered-down individually by pwad and pwda1/2 bits. these bits do not initialize the internal register values. when pwad b it = ?0?, the sdto1 pin goes to ?l?. wh en pwda bit = ?0?, the dac1/2 outputs go to 0v. as some click noise occurs, the analog output should be muted externally if the click noise influences system application. a dc internal state clock in mclk,lrck,bick a dc in (analog) a dc out (digital) dac internal state dac in (digital) dac out (internal status) mt1n/2n pin or mt1n/2n bit mute on (10) power-down don?t care gd ?0?data power-down ?0?data gd (5) (5) (6) (8) (9) 40/fs init cycle normal operation (3) gd normal operation gd (7) (4) mute on ?0?data ?0?data don?t care (8) (2) pdn power (1) (12) 0v cvee 0v cvee pin lout1,rout1/lout2 ,rout2 pins 0v mute mute normal 0v (10) (11) (11) 5/fs figure 7. power-up/down sequence example notes: (1) the timing of the pdn pin ?l? ? ?h? should be after the all powers (dvdd, avdd1/2 and cvdd1) are supplied. the ak4686 requires 150ns or longer ?l? period for the reset. supply the power during the pdn pin = ?l?.
[ak4686] ms1243-e-01 2010/10 - 24 - (2) power-on the charge pump circuit: pdn pin = ?l? ? ?h? & mclk1 or mclk2 is input. cvee pin becomes to the same voltage as cvee1/2 within about 5.3ms(fs=48khz). note: if the pwad, pwda1 and pwda2 b its are set to ?1? when the charge -pump is power-on, adc, dac1 and dac2 are initialized after the charge-pump1 circuit is powered-on. (3) the analog block of adc is initialized after exiting the power-down state. (4) the analog block of dac is initialized after exiting the power-down state. (5) digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay (gd). (6) adc outputs ?0? data in power-down state. (7) click noise occurs at the end of initialization of the anal og block. mute the digital outputs externally if the click noise influences system application. (8) click noise occurs at the falling edge of pdn and 512/fs after the rising edge(after charge-pump is powered-on) of pdn. (9) the cvee pin becomes 0v according to the time consta nt of the capacitor at th e cvee pin and the internal resistor. the internal resistor is 17.5k (typ.). charge pump circuit can be powered-up during this period. (10) amts1-0 bits control the soft mute transition time. when releasing the mute, the maximum dc offset is 20mv (at design value). this transition is a soft tr ansition so that no clicking noise occurs. (11) maximum 5mv dc offset is generated when power up the lineout circuit. more than 5.3ms(fs=48khz)+2msec interval (after 2msec from falling edge of cvee)is needed from a falling edge of pdn signal to a mute release to prevent a click noise. (12) charge pump circuit power down: pdn pin = ?h? ? ?l? the cvee pin becomes 0v accord ing to a flying capacitor and internal re sistor. the internal resister is 50k (typ). therefore, when the cvee pin has a flying capacitor of 2.2f, the time constant is 110ms (typ).
[ak4686] ms1243-e-01 2010/10 - 25 - reset function when rstn bit = ?0?, adc and dacs are powered-down but the internal re gister are not initialized. the dac1/2 outputs become 0v and the sdto1 pin outputs ?l?. as some click noise occurs, the analog output should be muted externally if the click noise influences system application. the figure 8 shows the power-up sequence. a dc internal state rstn bit normal operation digital block power-down normal operation gd gd a dc in (analog) ?0?data a dc out (digital) normal operation normal operation dac internal state ?0?data dac in (digital) dac out (analog) gd gd (2) (2) (3) (4) (6) (6) internal rstn bit digital block power-down 1~2/fs 4~5/fs (7) (5) 516/fs init cycle (1) notes: (1) the analog block of adc is initialized after exiting the reset state. (2) digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay (gd). (3) adc outputs ?0? data in power-down state. (4) click noise occurs at the end of initialization cycle of adc. mute the digital output externally if the click noise influences system application. (5) when rstn bit = ?0?, th e analog outputs become 0v. (6) click noise occurs in 4 5/fs after rstn bit becomes ?0?, and occurs in 1 2/fs after rstn bit becomes ?1?. this noise is output even if ?0? data is input. (7) there is a delay about 4~5/fs from rstn bit ?0? to the internal rstn bit ?0?. figure 8. reset sequence example
[ak4686] ms1243-e-01 2010/10 - 26 - serial control interface the ak4686 supports fast-mode i 2 c-bus system (max: 400khz). 1. data transfer in order to access any ic devices on the i 2 c bus, input a start condition first, fo llowed by a single slave address which includes the device address. ic devices on the bus compare this slave address with their own addresses and the ic device which has an identical address w ith the slave-address generates an ack nowledgement. an ic device with the identical address then executes either a read or write op eration. after the command execution, input a stop condition. 1-1. data change change the data on the sda line while scl line is ?l?. sda line condition must be stable and fixed while the clock is ?h?. change the data line condition between ?h? and ?l? only when the clock signal on the scl line is ?l?. change the sda line condition while scl line is ?h? only when the start condition or stop condition is input. scl sda data line stable : data valid change of data a llowed figure 9. data transfer 1-2. start condition and stop condition a start condition is generated by the tran sition of ?h? to ?l? on the sda line while the scl line is ?h?. all instructions are initiated by a start condition. a stop condition is generate d by the transition of ?l? to ?h? on sda line while scl line is ?h?. all instructions end by a stop condition. scl sda stop condition start condition figure 10. start and stop conditions
[ak4686] ms1243-e-01 2010/10 - 27 - 1-3. acknowledge an external device that is sending data to the ak4686 releas es the sda line (?h?) after receiving one-byte of data. an external device that receives data from the ak4686 then sets the sda line to ?l? at the next clock. this operation is called ?acknowledgement?, and it enables ve rification that the data transfer ha s been properly executed. the ak4686 generates an acknowledgement upon receipt of a start cond ition and slave address. for a write instruction, an acknowledgement is generated whenever receipt of each byte is completed. for a read instruction, succeeded by generation of an acknowledgement, the ak4686 releases the sd a line after outputting data at the designated address, and it monitors the sda line condition. when the master side generates an acknowledgement without sending a stop condition, the ak4686 outputs data at the next address location. when no acknowledgement is generated, the ak4686 ends data output (not acknowledged). scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition clock pulse for acknowledge not acknowledge figure 11. acknowledge on the i 2 c-bus 1-4. first byte the first byte which includes the slave-address is input after th e start condition is set, and a target ic device that will be accessed on the bus is selected by the slav e-address. the slave-address is configur ed with the upper 7-bits. data of the upper 5-bits is ?00100?. the next 2 bits are address bits that select the desired ic, and these cad1 and cad0 bits are fixed to ?10?. when the slave-address is inputted, an external device that has the identical device address generates an acknowledgement and instructions are then executed. the 8 th bit of the first byte (lowest bit) is allocated as the r/w bit. when the r/w bit is ?1?, the read instruction is executed , and when it is ?0?, the write instruction is executed. 0 0 1 0 0 cad1 cad0 r/w figure 12. the first byte
[ak4686] ms1243-e-01 2010/10 - 28 - 2. write operations set r/w bit = ?0? for the write operation of the ak4686. after receipt of the start condition and the first byte, the ak 4684 generates an acknowledge, and awaits the second byte (register address). the second byte consists of the address for control registers of ak4686. the format is msb first, and those most significant 3-b its are ?don?t care?. * * * a4 a3 a2 a1 a0 (*: don?t care) figure 13. the second byte after receipt of the second byte, the ak 4686 generates an acknowledge, and awaits the third byte. those data after the second byte contain control data. the format is msb first, 8bits. d7 d6 d5 d4 d3 d2 d1 d0 figure 14. byte structure after the second byte the ak4686 is capable of more than one byte write operation by one sequence. after receipt of the third byte , the ak4686 generates an acknowledge, and aw aits the next data again. the master can transmit more than one data word instead of terminating the wr ite cycle after the first data word is transferred. after the receipt of each data, the internal 5bits address counter is increm ented by one, and the next data is taken into next address automatically. if the address exceeds 05h prior to generating th e stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. sda s t a r t a c k a c k s slave a ddress a c k register a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) figure 15. write operation
[ak4686] ms1243-e-01 2010/10 - 29 - 3. read operations set r/w bit = ?1? for the read operation of the ak4686. the master can read next address?s data by generating the acknowledge instead of terminating the write cycle after the receipt of the first data word. after the receipt of each data, the internal 5bits ad dress counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 0dh prior to generating stop condition, the address counter will ?roll ov er? to 00h and the previous data will be overwritten. the ak4686 supports two basic read operations: current address read and random read. 3-1. current address read the ak4686 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address ?n?, the next current read operation would access data from the address ?n+1?. after receipt of the slave address with r/w bit set to ?1?, the ak4686 generates an acknowledge, transmits 1byte data, which address is set by the internal addr ess counter, and increments the internal address counter by 1. if the master does not generate an acknowledge but generate stop condition, the ak4686 discontinues transmission sda s t a r t a c k a c k s slave a ddress a c k data(n) data(n+1) p s t o p data(n+x) a c k data(n+2) figure 16. current address read 3-2. random read random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues start condition, slave address(r/w bit=?0?) and th en the register address to read. after the register address?s acknowledge, the master immediately reissues the st art condition and the slave address with the r/w bit set to ?1?. then the ak4686 generates an acknowledge, 1byte data and increments the internal ad dress counter by 1. if the master does not generate an acknowledge but generate the stop condition, the ak4686 discontinues transmission. sda s t a r t a c k a c k s s s t a r t slave a ddress word a ddress(n) slave a ddress a c k data(n) a c k p s t o p data(n+x) a c k data(n+1) figure 17. random read
[ak4686] ms1243-e-01 2010/10 - 30 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h powerdown 1 0 0 0 0 0 mt2n mt1n rstn 01h powerdown 2 0 pwda2 pwda1 pwad 0 acks2 dfs21 dfs20 02h audio data format 0 0 0 0 dif21 dif20 dif11 dif10 03h de-emphasis/ att speed dem21 dem20 dem11 dem10 0 0 0 0 04h clock control 0 acks1 dfs11 dfs10 0 cks12 cks11 cks10 05h input selector control & analog mute control 0 amts2 amts1 amts0 ain3 ain2 ain1 ain0 note: for addresses from 06h to 1fh, data must not be written. when the pdn pin is set to ?l?, the regist ers are initialized to their default values. when rstn bit is set to ?0?, the internal timing is rese t, but registers are not initialized to their default values. the bits defined as 0 must contain a "0" value.
[ak4686] ms1243-e-01 2010/10 - 31 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h powerdown 1 0 0 0 0 0 mt2n mt1n rstn r/w rd rd rd rd rd r/w r/w r/w default 0 0 0 0 0 0 0 1 rstn: codec initial timing reset 0: reset. registers are not initialized. 1: normal operation (default) mt1n: dac1 mute control 0: mute (default) 1: normal output mt2n: dac2 mute control 0: mute (default) 1: normal output mt1n: dac1 analog soft mute control mt1n pin mt1n bit dac1analog mute status l 0 mute l 1 mute (default) h 0 mute (default) h 1 unmute table 20. dac1 analog mute control mt2n: dac2 analog soft mute control mt2n pin mt2n bit dac2 analog mute status l 0 mute l 1 mute (default) h 0 mute (default) h 1 unmute table 21. dac1 analog mute control
[ak4686] ms1243-e-01 2010/10 - 32 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h powerdown 2 0 pwda2 pwda1 pwad 0 acks2 dfs21 dfs20 r/w rd r/w r/w r/w rd r/w r/w r/w default 0 1 1 1 0 0 0 0 dfs21-20: port2(dac2) sampling speed control these settings are ignored in auto setting mode. refer to table 9 . acks2: port2(dac2) auto setting mode control 0: disable, manual setting mode (default) 1: enable, auto setting mode master clock frequency is detected automatically wh en acks2 bit =?1?. in this case, the dfs21-20 bits are ignored. when this bit is ?0?, dfs21-20 bits set the sampling speed mode. pwad: power-down control of adc 0: power-down 1: normal operation (default) pwda1: full-power-down control of dac1 0: power-down 1: normal operation (default) pwda2: full-power-down control of dac2 0: power-down 1: normal operation (default)
[ak4686] ms1243-e-01 2010/10 - 33 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h audio data format 0 0 0 0 dif21 dif20 dif11 dif10 r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 1 1 1 1 dif21-20: audio format control for port2 refer to table 17 . dif11-10: audio format control for port1 refer to table 16 . addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h de-emphasis/ att speed dem21 dem20 dem11 dem10 0 0 0 0 r/w r/w r/w r/w r/w rd rd rd rd default 0 1 0 1 0 0 0 0 dem11-10: dac1 de-emphasis filter control dem21-20: dac2 de-emphasis filter control refer to table 15 . addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h clock control 0 acks1 dfs11 dfs10 0 cks12 cks11 cks10 r/w rd r/w r/w r/w rd r/w r/w r/w default 0 0 0 0 0 0 0 0 cks12-10: port1(adc&dac1) clock control in master mode. refer to table 2 . dfs11-10: port1(adc&dac1) sampling speed control these settings are ignored in auto setting mode. refer to table 3 . acks1: port1(adc&dac1) auto setting mode 0: disable, manual setting mode (default) 1: enable, auto setting mode master clock frequency is detected automatically wh en ack1s bit =?1?. in this case, the dfs11-10 bits are ignored. when this bit is ?0?, dfs11-10 bits set the sampling speed mode.
[ak4686] ms1243-e-01 2010/10 - 34 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h input selector control & analog mute control 0 amts2 amts1 amts0 ain3 ain2 ain1 ain0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 0 0 0 ain3-0: adc input selector control 0000: lin1/rin1 (default) 0001: lin2/rin2 0010: lin3/rin3 0011: lin4/rin4 0100: lin5/rin5 0101: lin6/rin6 1xxx: mute (x: don?t care) amts2-0: analog mute clock source control default: ?001? refer to table 18 .
[ak4686] ms1243-e-01 2010/10 - 35 - system design figure 18 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. ak4686 a nalog ground digital ground micro controller audio dsp1 analog in 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 lin5 rin5 vss1 lout1 rout1 lout2 rout2 a vdd2 lin4 nc rin3 lin3 nc rin2 lin2 nc rin1 lin1 vss2 cvee cn vss3 cp cvdd pdn sdti2 lrck2 mclk2 bick2 nc scl sda bick1 lrck1 sdto vss4 dvdd mt1n mclk1 sdti1 ms1 mt2n nc lin6 rin6 a vdd1 nc rin4 digital audio dsp2 2.2u 2.2u 10u + 0.1u 3.3v analog + 10u 0.1u + 10u 0.1u 3.3v digital + 10u 0.1u 3.3v analog 3.3v analog figure 18. typical connection diagram (slave mode) notes: - vss1, vss2, vss3, and vss4 must be conn ected to the same an alog ground plane.
[ak4686] ms1243-e-01 2010/10 - 36 - 1. grounding and power supply decoupling the ak4686 requires careful attention to power supply and grounding arrangements. avdd1, avdd2, dvdd and cvdd are usually supplied from analog supply in system. if avdd1, avdd2, dvdd, and cvdd are supplied separately, it is recommended to power-up dvdd first to avoid a click noise. vss1, vss2, vss3 and vss4 of the ak4686 must be connected to analog ground plane. system analog ground and digital ground must be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4686 as possible, with the small va lue ceramic capacitor being the nearest. 2. voltage reference inputs the voltage of avdd1 sets the adc input range, and avdd1 (avdd2) sets the dac1(dac2) analog output range. a 0.1 f ceramic capacitor should be attached between the avdd1/2 pin and vss1/2 pin. 3. analog inputs the ak4686 receives the analog input thr ough the single-ended pre-amp. the input range is 2.2 x avdd1/3.3 vrms (typ. fs=48khz) at each analog input pins. each input pins are bias ed to 0v(typ) internally. the adc output data format is 2?s complement. the internal digital hpf removes the dc offset. the ak4686 samples the analog inputs at 64fs. the digital filte r rejects noise above the stop band except for multiples of 64fs. the ak4686 includes an anti-aliasing filter (rc filter) to attenuate a noise around 64fs. lin1-6, rin1-6 ak4686 2.0vrms analog in figure 19. external circuit example1 4. analog outputs the analog outputs are also single-ended and centered on 0v (t yp). the output signal range scal es with the supply voltage and nominally 2 x avdd2(avdd3)/3.3 vrms at each analog output pins. the da c1(dac2) input data format is 2?s complement. the output voltage is a positive full s cale for 7fffffh(@24bit) and a negative full scale for 800000h(@24bit). the ideal output is 0v for 000000h(@24bit). the internal analog filters (scf and ctf) remove most of the noise generated by the delta-sigma modulator of dac1(dac2) beyond the audio passband. the dc offsets on analog outputs are typically 0v. lout1/2, rout1/2 470 ak4686 2.0vrms (typ) analog out figure 20. external circuit example1 5. attention to the pcb wiring attention should be given to avoid coupling with other signals on each analog input/output pins. unused input pins among lin1-6 and rin1-6 pins must be left open.
[ak4686] ms1243-e-01 2010/10 - 37 - package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 48pin lqfp(unit: mm) 0.10 37 24 25 36 0.09 0.20 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 0.30 ~ 0.75 0.5 m material & lead finish package molding compound: epoxy, halogen (bromine and chlorine) free lead frame material: cu lead frame surface treatment : solder (pb free) plate
[ak4686] ms1243-e-01 2010/10 - 38 - marking ak4686eq xxxxxxx 1 1) pin #1 indication 2) asahi kasei logo 3) marking code: ak4686eq 4) date code: xxxxxxx (7 digits) date (yy/mm/dd) revision reason page contents 10/10/05 00 first edition 10/10/25 01 specification change 7 analog characteristics dac to analog output output voltage: 1.85 1.90vrms (min) revision history
[ak4686] ms1243-e-01 2010/10 - 39 - important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, a pplication circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the in corporation of these external circuits, app lication circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor au thorized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no resp onsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in wh ich its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, disp oses of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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